Bonding pad design

ABSTRACT

A bonding pad for an integrated circuit, having a conductive base layer. The conductive base layer has slots formed in it, where the slots extend completely through the conductive base layer. An insulating layer is disposed on top of the conductive base layer. The insulating layer protrudes into the slots of the conductive base layer. The insulating layer also includes a low k material. A conductive top layer is disposed on top of the insulating layer.

FIELD

[0001] This invention relates to the field of integrated circuitmanufacturing. More particularly, the invention relates to the designand manufacture of bonding pads for an integrated circuit.

BACKGROUND

[0002] As the industry continues to advance, integrated circuitscontinue to become more complex, incorporate more components, operate athigher speeds, and are contained within a smaller area on the substrate.Consequently, it becomes increasingly important to effectively isolatecomponents one from another so as to reduce undesired phenomena, such asinterconnect capacitance, which impede the performance of the integratedcircuit.

[0003] With respect to the design and manufacture of bonding pads,layers of low k materials, which have relatively low dielectricconstants in comparison to other nonconductive materials used in theintegrated circuit, are effective in isolating adjacent conductors andreducing capacitance.

[0004] Unfortunately, however, the incorporation of low k dielectricsinto bonding pads has proved to be problematic in other aspects. Low kmaterials are typically significantly softer and weaker than higher kmaterials, and when force is applied to the bonding pad, such as duringprobing or bonding, the layers of low k material tend to crack andfracture. These fractures tend to propagate through the dielectriclayers and may even result in delamination of the dielectric layer orthe entire bonding pad.

[0005] What is needed, therefore, is a bonding pad that provides boththe isolation benefits of low k dielectric materials and sufficientstrength to resist cracking and fracturing.

SUMMARY

[0006] The above and other needs are met by a bonding pad for anintegrated circuit, having a conductive base layer. The conductive baselayer has slots formed in it, where the slots extend completely throughthe conductive base layer. An insulating layer is disposed on top of theconductive base layer. The insulating layer protrudes into the slots ofthe conductive base layer. The insulating layer also includes a low kmaterial. A conductive top layer is disposed on top of the insulatinglayer.

[0007] The bonding pad as described above allows the incorporation ofthe low k material between layers of the bonding pad while minimizingthe inherent softness of the low k layer. When the low k insulatinglayer is formed, most of the low k material is disposed in the slots ofthe conductive base layer. These slots also tend to reduce the amount oflow k material that tends to build up in the center of a large area thatis covered with low k material. Thus, the slots not only contain most ofthe low k material, but prevent additional build up of low k material inthe center of the conductive base layer. In this manner, there is areduced thickness of low k material between the conductive base layerand the conductive top layer of the bonding pad, which tends tostrengthen the overall structure of the bonding pad. However, thebenefits of the use of the low k material between the conductive baselayer and the conductive top layer of the bonding pad are retained.

[0008] In various preferred embodiments the bonding pad includes aplurality of vias extending through the insulating layer andelectrically connecting the conductive base layer to the conductive toplayer at peripheral portions of the conductive base layer and theconductive top layer. The insulating layer preferably includes a baseoxide layer on top of the conductive base layer, a low k dielectriclayer on top of the base oxide layer, and a cap oxide layer between thelow k dielectric layer and the conductive top layer.

[0009] Both the conductive base layer and the conductive top layerpreferably include a metal such as aluminum, copper, nickel, ruthenium,titanium, tungsten, platinum, and gold. The slots of the conductive baselayer preferably form a pattern of substantially parallel slots, havinga width of about eleven microns and a spacing of about three microns.The slot width and number of slots preferably depend at least in part onthe thickness and the size of the bonding pad. The insulating layerpreferably has a thickness, as measured between the conductive baselayer and the conductive top layer, of from about five thousandangstroms to about fifteen thousand angstroms.

[0010] According to another aspect of the invention, there is providedan integrated circuit having the bonding pad of claim 1. A method offorming the bonding pad is also described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Further advantages of the invention are apparent by reference tothe detailed description when considered in conjunction with thefigures, which are not to scale so as to more clearly show the details,wherein like reference numbers indicate like elements throughout theseveral views, and wherein:

[0012]FIG. 1 is a top plan view of a conductive base layer of a bondingpad according to a first embodiment of the present invention,

[0013]FIG. 2 is a cross sectional view of a portion of the bonding padstructure to the first embodiment of the present invention, and

[0014]FIG. 3 is a detailed cross sectional view of a portion of thebonding pad, showing a composite dielectric layer according to apreferred embodiment of the invention.

DETAILED DESCRIPTION

[0015] Referring now to FIG. 1, there is depicted a top plan view of abonding pad 10 according to a preferred embodiment of the invention. Thebonding pad 10 is formed as part of an integrated circuit 12. Asdepicted in FIG. 1, the bonding pad 10 comprises most of the integratedcircuit 10. However, this depiction is representational only. In actualembodiments, the bonding pad 10 is fairly small in comparison to thebalance of the integrated circuit 12. Further, in actual embodimentsthere are preferably many bonding pads 10 formed in the integratedcircuit 12. Further, the active and other circuit elements of theintegrated circuit 12 have been omitted from FIG. 1, so as to not undulydistract from the depiction of the bonding pad 10. Thus, the depictionof FIG. 1 is intended to highlight the more relevant portions of theintegrated circuit 12 in light of the present invention, to facilitatethe description and understanding of the invention.

[0016] As best seen in FIG. 2, the bonding pad 10 is formed in part of aconductive base layer 14 and a conductive top layer 20. Between theconductive base layer 14 and the conductive top layer 20 is aninsulating layer 22. The conductive base layer 14 has slots 16 formed init, which slots 16 preferably extend completely through the conductivebase layer 14. Electrically conductive vias 18 electrically connect theconductive base layer 14 to the conductive top layer 20. Theelectrically conductive vias 18 also preferably electrically connect theconductive base layer 14 and the conductive top layer 20 to lower layers24, some of which are electrically conductive, and some of which areelectrically insulating. It is appreciated that there may be a greateror lesser number of lower layers 24 than depicted in FIG. 2, and thestructure as depicted in FIG. 2 is in this regard representational only.It is also appreciated that the embodiments as described below can beapplied to one or more of the lower levels 24.

[0017] The conductive base layer 14 and the conductive top layer 20 arepreferably formed of a metal such as aluminum, tantalum, gold, copper,platinum, ruthenium, or titanium. It is appreciated that the recitationof such metals as used herein includes various alloys and nitrides ofthe metals, as applicable to the specific structure being described. Itis also appreciated that such layers are often formed in multiplelayers, which include adhesion, anti-reflection, and diffusion barrierlayers of different materials, and which are formed to act cooperativelywith the conduction layer that is also formed. Thus, the recitation of aspecific material herein is intended to be representative and notexclusive of the various materials that can be used to form thestructure.

[0018] The conductive base layer 14 is preferably formed as a contiguouslayer, after which the slots 16 are etched through the conductive baselayer 14 in a wet or dry etch procedure. Alternately, the conductivebase layer 14 is originally formed with the slots 16, such as with alift off deposition process. The conductive base layer 14 is preferablybetween about three thousand angstroms and about twenty thousandangstroms in thickness, and most preferably about ten thousand angstromsthick. The slots 16 formed in the conductive base layer 14 arepreferably between about five microns and about twenty microns in width,and are most preferably about eleven microns in width. The bars of theconductive base layer 14 that are left between the slots 16 arepreferably about one micron to about ten microns in width, and mostpreferably about three microns in width.

[0019] The dimensions and shape of the bonding pad do not necessarilyconstitute a square feature, but can take on other shapes, such as arectangle or a circle. The bonding pad 10 is preferably between aboutfifty microns and about one hundred and fifty microns square, and mostpreferably about eighty-five microns square. The slots 16 preferablyhave a length of between about twenty-five microns and about one hundredand thirty-five microns, and most preferably about sixty-nine microns.It is appreciated that the preferred dimensions as given above arerepresentational, and highly dependent upon the technology to which thepresent invention is applied.

[0020]FIG. 3 depicts a portion of the bonding 10 in greater detail.Depicted are two of the bars of the conductive bottom layer 14 in crosssection, and detail of a preferred embodiment of the insulating layer 22that is formed between the conductive bottom layer 14 and the conductivetop layer 20, especially in the region of the slot 16 between the twobars of the conductive bottom layer 14. In various preferredembodiments, the insulating layer 22 includes layers of electricallyinsulating materials such as oxides like silicon dioxide, nitrides likesilicon nitride, and most preferably a variety of materials that tend toexhibit dielectric constants that are lower then those typicallyassociated with silicon dioxide, which materials are generally referredto as low k materials.

[0021] In a most preferred embodiment, the insulating layer 22 is formedwith a base oxide layer 22 a on top of the conductive base layer 14. Thebase oxide layer 22 a preferably has a thickness of between abouttwenty-five angstroms and about three thousand angstroms, and mostpreferably about five hundred angstroms. The base oxide layer 22 a ismost preferably a relative hard material, such as silicon dioxide. Thebase oxide layer 22 a may be formed according to a variety of processes,such as sputter deposition or chemical vapor deposition, and is mostpreferably a relatively conformal layer, indicating that it has a fairlyuniform thickness.

[0022] A low k dielectric layer 22 b is preferably formed on top of thebase oxide layer 22 a. As depicted in FIG. 3, the low k dielectric layer22 b preferably fills in most of the slot 16 between the bars of theconductive base layer 14. Thus, the thickness of the low k dielectriclayer 22 b in the slot 16 is preferably between about two thousandangstroms and about twelve thousand angstroms, and most preferably aboutsix thousand angstroms, and the thickness of the low k dielectric layer22 b above the bars of the conductive base layer 24 is preferablybetween about zero angstroms and about twelve thousand angstroms, andmost preferably about five hundred angstroms. Thus, the thickness of thelow k dielectric layer 22 b is most preferably not uniform.

[0023] The planarity of the low k dielectric layer 22 b may be formed ina variety of different processes. For example, in one embodiment the lowk dielectric layer 22 b is a material such as a polyamide that is formedby spinning the material onto the substrate. In other embodiments thelow k dielectric layer 22 b can be deposited using chemical vapordeposition. Other processes that are compatible with the specificmaterials used for the various layers may also be employed.

[0024] The low k dielectric layer 22 b tends to be relatively soft, andthe slots 16 limit the build up of the low k dielectric layer 22 bbetween the bars of the conductive base layer 14. The low k film 22 babove the bars of the conductive base layer 14 is significantly lessthick than the harder silicon dioxide layer 22 c, thus providestructural support to the conductive top layer 20, which tends to reducethe occurrence and degree of cracking and other stress failures of thebonding pad 10 during probing and bonding.

[0025] The low k dielectric layer 22 b is preferably overlaid with a capoxide layer 22 c. After planarization the cap oxide layer 22 cpreferably has a thickness above layer 14 of between about threethousand angstroms and about fifteen thousand angstroms, and mostpreferably about nine thousand angstroms. The cap oxide layer 22 c ismost preferably a relative hard material, such as silicon dioxide. Thecap oxide layer 22 c may be formed according to a variety of processes,such as sputter deposition or chemical vapor deposition, and is mostpreferably a relatively conformal layer, indicating that it has a fairlyuniform thickness as deposited above the low k film 22 b.

[0026] Thus, in the embodiment depicted in FIG. 3, the greater portionof the thickness of the insulating layer 22 between the bars of theconductive bottom layer 14 and the conductive top layer 20 is therelatively harder bottom oxide layer 22 a and cap oxide layer 22 c. Thistends to provide structural support to the conductive top layer 20, asdescribed above. The thickness of the insulating layer 20 between thetop of the bars of the conductive base layer 14 and the conductive toplayer 20 is preferably between about three thousand angstroms and aboutfifteen thousand angstroms, and most preferably about ten thousandangstroms.

[0027] However, the greater portion of the thickness of the insulatinglayer 22 in the slots 16 of the conductive bottom layer 14 beneath theconductive top layer 20 is the cap oxide layer 22 c. This tends toincrease the hardness and strength of the film below the bonding pad 20.If a crack is initiated during the bonding operation, the propagation ofthe crack is preferably limited to the segmented area 16. To furtherstrengthen the bonding pad stack, a series of vias can be added toconnect metal lines 14 to the bonding pad layer 20. The thickness of thelow k dielectric layer 22 b in the slots 16 of the conductive base layer14 is preferably between about three thousand angstroms and about tenthousand angstroms, and most preferably about six thousand angstroms.

[0028] The foregoing description of preferred embodiments for thisinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise form disclosed. Obvious modifications orvariations are possible in light of the above teachings. The embodimentsare chosen and described in an effort to provide the best illustrationsof the principles of the invention and its practical application, and tothereby enable one of ordinary skill in the art to utilize the inventionin various embodiments and with various modifications as is suited tothe particular use contemplated. All such modifications and variationsare within the scope of the invention as determined by the appendedclaims when interpreted in accordance with the breadth to which they arefairly, legally, and equitably entitled.

What is claimed is:
 1. A bonding pad for an integrated circuit, thebonding pad comprising: a conductive base layer having slots formedtherein, the slots extending completely through the conductive baselayer, an insulating layer disposed on top of the conductive base layer,the insulating layer protruding into the slots of the conductive baselayer, and the insulating layer including a low k material, and aconductive top layer disposed on top of the insulating layer.
 2. Thebonding pad of claim 1 further comprising a plurality of vias extendingthrough the insulating layer and electrically connecting the conductivebase layer to the conductive top layer at peripheral portions of theconductive base layer and the conductive top layer.
 3. The bonding padof claim 1 wherein the insulating layer comprises a base oxide layer ontop of the conductive base layer, a low k dielectric layer on top of thebase oxide layer, and a cap oxide layer between the low k dielectriclayer and the conductive top layer.
 4. The bonding pad of claim 1wherein both the conductive base layer and the conductive top layercomprise a metal selected from the group consisting of aluminum, copper,nickel, ruthenium, titanium, tungsten, platinum, and gold.
 5. Thebonding pad of claim 1 wherein the slots of the conductive base layercomprise a pattern of substantially parallel slots.
 6. The bonding padof claim 1 wherein the slots of the conductive base layer have a widthof about eleven microns and a spacing of about three microns.
 7. Thebonding pad of claim 1 wherein the insulating layer has a thicknessmeasured between the conductive base layer and the conductive top layerof from about three thousand angstroms to about fifteen thousandangstroms.
 8. The bonding pad of claim 1 further comprising multiplelayers of the conductive base layer and the overlying insulating layerbelow the conductive top layer.
 9. An integrated circuit, theimprovement comprising the bonding pad of claim
 1. 10. A method forforming a bonding pad on a substrate, the method comprising the stepsof: forming a conductive base layer on the substrate, the conductivebase layer having slots extending completely through the conductive baselayer, forming an insulating layer on top of the conductive base layer,the insulating layer protruding into the slots of the conductive baselayer, and the insulating layer including a low k material, and forminga conductive top layer on top of the insulating layer.
 11. The method ofclaim 10 further comprising the step of forming a plurality ofconductive vias extending through the insulating layer and electricallyconnecting the conductive base layer to the conductive top layer atperipheral portions and adjacent the slots of the conductive base layerand the conductive top layer.
 12. The method of claim 10 wherein thestep of forming the insulating layer comprises the steps of: forming abase oxide layer on top of the conductive base layer, forming a low kdielectric layer on top of the base oxide layer, and forming a cap oxidelayer between the low k dielectric layer and the conductive top layer.13. The method of claim 10 wherein both the conductive base layer andthe conductive top layer comprise a metal selected from the groupconsisting of aluminum, copper, nickel, ruthenium, titanium, tungsten,platinum, and gold.
 14. The method of claim 10 wherein the slots of theconductive base layer comprise a pattern of substantially parallelslots.
 15. The method of claim 10 wherein the slots of the conductivebase layer have a width of about eleven microns and a spacing of aboutthree microns.
 16. The method of claim 10 wherein the insulating layerhas a thickness measured between the conductive base layer and theconductive top layer of from about three thousand angstroms to aboutfifteen thousand angstroms.
 17. The method of claim 10 furthercomprising forming multiple layers of the conductive base layer and theoverlying insulating layer below the conductive top layer.
 18. Anintegrated circuit, the improvement comprising a bonding pad formedaccording to the method of claim
 10. 19. An integrated circuit, theimprovement comprising a bonding pad having: a conductive base layerhaving slots formed therein, the slots extending completely through theconductive base layer, an insulating layer disposed on top of theconductive base layer, the insulating layer protruding into the slots ofthe conductive base layer, and the insulating layer including a low kmaterial, and a conductive top layer disposed on top of the insulatinglayer.
 20. The integrated circuit of claim 19 wherein the insulatinglayer comprises a base oxide layer on top of the conductive base layer,a low k dielectric layer on top of the base oxide layer, and a cap oxidelayer between the low k dielectric layer and the conductive top layer.21. The integrated circuit of claim 19 wherein the slots of theconductive base layer have a width of about eleven microns and a spacingof about three microns.
 22. The integrated circuit of claim 19 whereinthe insulating layer has a thickness measured between the conductivebase layer and the conductive top layer of from about three thousandangstroms to about fifteen thousand angstroms.
 23. The integratedcircuit of claim 19 further comprising multiple layers of the conductivebase layer and the overlying insulating layer below the conductive toplayer.